This invention relates to carrier recovery apparatuses for phase-modulated waves including phase-locked loops (PLLs), and more particularly to carrier recovery apparatuses capable of eliminating false locks.
In conventional carrier recovery apparatuses for N-phase phase-modulated waves, the PLLs are generally used to recover a stable carrier. Such carrier recovery apparatuses often have a false lock of the PLL, i.e. a phase-synchronization of the loop with a frequency different from that of an input carrier. The false lock causes the phase of the recovered carrier, which gives a reference phase for the synchronous detection, to be fixed to a value other than the reference. Since frequency beats corresponding to the difference between the reference phase and false-locked phase are superimposed on the demodulated output, normal demodulation is made impossible.
The lock usually occurs when (1) the delay time in the PLL is unignorably long or (2) the PLL is either a sampling-controlled system or equivalent thereto. In most instances, item (2) is a more troublesome factor. The false lock due to item (1) can be avoided by sufficiently reducing the delay time in the PLL. However, an N-phase phase-modulated wave, even in the absence of sampling control, is inevitably subjected to the false lock to some extent. The false lock can only be averted at the sacrifice of PLL performance, for instance by decreasing the loop gain . Thus, the false lock affects substantially the stability of the carrier recovery apparatus.
A false lock due to the item (2) arises at a frequency offset linked to the modulation rate (sampling frequency f.sub.s), and generally occurs at a frequency .+-.m/n f.sub.s (where m and n are integers, and m/n is irreducible) apart from the input carrier frequency (f.sub.o). N-phase phase-demodulated waves are more susceptible to false locks at a frequency offset of .+-.m/N f.sub.s (where m is a positive integer), particularly so when m equals 1. Consequently, affected by the adjoining false locks, a desired lock range may be narrowed, or even reversed in extreme cases. This is particularly conspicuous in the instances of increased phases or decreased modulation rate, where the desired lock range cannot be secured, resulting in a serious impediment to loop design.
One conceivable way to avoid such false lock is to detect an automatic phase control (APC) signal of the PLL with a beat detector or the like, distinguish between the desired and false locks according to this detection output, give a sweep voltage to a voltage-controlled oscillator (VCO) of the PLL for a certain period of time, and thereby lead the loop into a desired synchronized state. However, since this method depends on the detection of the noise level of the APC signal for distinguishing between the desired and false locks, it is difficult to determine the noise level difference, on account of frequency pattern jitters, where the input phase-modulated wave is a multi-phase modulated wave subjected to strict band restriction (for instance, roll-off shaping). Nor is stable detection possible where the signal to noise (S/N) ratio of the input is low. Moreover, the sweep voltage to control the VCO has to cover both the positive and negative ranges because it is impossible to determine whether the frequency offset of the false lock is positive or negative. Therefore, the method takes an unnecessarily long time for locking and requires a complex control circuit to generate the sweep signal, which involves a reliability problem on account of its complexity.
Besides this method, there is another control circuit utilizing the impedance difference between the synchronized and unsynchronized states of the phase synchronization loop as viewed from outside (see U.S. Pat. No. 4,121,166). The control circuit has a low-frequency oscillator in addition to the VCO in the PLL. When a signal from the low-frequency oscillator is injected into the PLL, it causes the VCO to sweep and expand the range of synchronization as the internal impedance of the loop is high when it is in an unsynchronized state. In a synchronized state, on the other hand, since the internal impedance of the loop is reduced and the injected signal is sufficiently compressed within the PLL, the injected signal will not affect the PLL. When an undesired synchronized state is caused by the false lock, any distinction between the desired and undesired synchronized state cannot be made because the internal impedance of the PLL drops even in the case of the undesired synchronized state. To avoid the undesired state, the low-frequency sweep circuit is actuated after a synchronized state has been recognized as opposed to an unsynchronized state, and a control voltage sweep of the VCO is continued for a certain period of time so that the desired synchronized state, out of the range of the false lock, can be stably attained.
This system, which cannot distinguish the undesired from the desired state, requires a sweep circuit separately from the low-frequency oscillator and, moreover, precise setting of the optimum sweep range, with the PLL parameter taken into account, so that the lock range of the desired synchronized state cannot be deviated from. This circuit involves another problem in that the complexity of its control means substantially affects the overall stability of the carrier recovery apparatus. Furthermore, it is impossible for the circuit to determine the polarity of the sweep, which has to be achieved at a sufficiently low frequency, resulting in an extremely long lock period.